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SFEPD154QXBWR-7237AN Specification.pdf
About this item SFEPD154QXBWR-7237AN
The 1.54 Inch 200x200 EPD 3 Color BWR E-paper Display with SPI Interface is a versatile electronic paper display designed for applications that demand low power consumption and clear visibility in various lighting conditions. Here's a detailed introduction to this product:
Product Overview:
Key Features:
Technical Specifications:
Applications:
This E-paper display is perfect for applications such as shelf labels, industrial instruments, and any scenario where a low-power, high-visibility display is required.
Mechanical Information
| Parameter | Specifications | Unit | Remark |
| Screen Size | 1.54 | Inch | |
| Display Resolution | 200(H)×200(V) | Pixel | Dpi:188 |
| Active Area | 27.0(H)×27.0(V) | mm | |
| Pixel Pitch | 0. 14×0. 14 | mm | |
| Pixel Configuration | Square | ||
| Outline Dimension | 31.80(H)×37.32(V) ×1.0(D) | mm | |
| Weight | 2. 18±0.5 | g |
Product Drawing

Interface Pin Definition
| No. | Name | I/O | Description | Remark |
| 1 | NC | Do not connect with other NC pins | Keep Open | |
| 2 | GDR | O | N-Channel MOSFET Gate Drive Control | |
| 3 | RESE | I | Current Sense Input for the Control Loop | |
| 4 | NC | Do not connect with other NC pins | Keep Open | |
| 5 | VSH2 | C | Positive Source driving voltage | |
| 6 | TSCL | O | This pin is I2C Interface to digital temperature sensor Clock pin. External pull up resistor is required when connecting to I2C slave. When not in use: Open | |
| 7 | TSDA | I/O | This pin is I2C Interface to digital temperature sensor Data pin. External pull up resistor is required when connecting to I2C slave. When not in use: Open | |
| 8 | BS1 | I | Bus Interface selection pin | |
| 9 | BUSY | O | Busy state output pin | |
| 10 | RES# | I | Reset signal input. Active Low. | |
| 11 | D/C# | I | Data /Command control pin | |
| 12 | CS# | I | Chip select input pin | |
| 13 | SCL | I | Serial Clock pin (SPI) | |
| 14 | SDA | I | Serial Data pin (SPI) | |
| 15 | VDDIO | P | Power Supply for interface logic pins It should be connected with VCI | |
| 16 | VCI | P | Power Supply for the chip | |
| 17 | VSS | P | Ground | |
| 18 | VDD | C | Core logic power pin VDD can be regulated internally from VCI. A capacitor should be connected between VDD and VSS | |
| 19 | VPP | P | Power Supply for OTP Programming. | |
| 20 | VSH1 | C | Positive Source driving voltage | |
| 21 | VGH | C | Positive Gate driving voltage. | |
| 22 | VSL | C | Negative Source driving voltage | |
| 23 | VGL | C | Negative Gate driving voltage. | |
| 24 | VCOM | C | VCOM driving voltage |
Absolute maximum rating
| Parameter | Symbol | Rating | Unit |
| Logic supply voltage | VCI | -0.5 to +6.0 | V |
| Logic Input voltage | VIN | -0.5 to VCI +0.5 | V |
| Logic Output voltage | VOUT | -0.5 to VCI +0.5 | V |
| Operating Temp range | TOPR | 0 to +40 | ºC |
| Storage Temp range | TSTG | -25 to+70 | ºC |
| Optimal Storage Temp | TSTGo | 23±2 | ºC |
| Optimal Storage Humidity | HSTGo | 55±10 | %RH |
Panel DC Characteristics
| Parameter | Symbol | Conditions | Applica ble pin | Min. | Typ. | Max | Units |
| Single ground | VSS | - | - | 0 | - | V | |
| Logic supply voltage | VCI | - | VCI | 2.2 | 3.0 | 3.7 | V |
| Core logic voltage | VDD | VDD | 1.7 | 1.8 | 1.9 | V | |
| High level input voltage | VIH | - | - | 0.8 VCI | - | - | V |
| Low level input voltage | VIL | - | - | - | - | 0.2 VCI | V |
| High level output voltage | VOH | IOH = -100uA | - | 0.9 VCI | - | - | V |
| Low level output voltage | VOL | IOL = 100uA | - | - | - | 0. 1 VCI | V |
| Typical power | PTYP | VCI =3.0V | - | - | 7.5 | - | mW |
| Deep sleep mode | PSTPY | VCI =3.0V | - | - | 0.003 | - | mW |
| Typical operating current | Iopr_VCI | VCI =3.0V | - | - | 2.5 | - | mA |
| Image update time | - | 25 ºC | - | - | 22 | - | sec |
|
Sleep mode current |
Islp_VCI | DC/DC off No clock No input load Ram data retain |
- |
- |
20 |
uA | |
|
Deep sleep mode current |
Idslp_VCI | DC/DC off No clock No input load Ram data not retain |
- |
- |
1 |
5 |
uA |
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